Fixes for NXP T2080 ports

[dgarske]

Fix wolfBoot boot on CW VPX3-152 (256 MB NOR flash variant)

Summary

Fixes a series of e6500/T2080 boot issues that prevented wolfBoot from booting on
the Curtiss-Wright VPX3-152 (256 MB NOR flash at 0xF0000000, CCSRBAR relocated
to 0xEF000000). NAII 68PPC2 (128 MB flash at 0xE8000000) is unaffected.

Root Causes Fixed

1. lis sign-extension on e6500 -- Multiple lis r,addr@h instructions in
   boot_ppc_start.S (CCSRBAR relocation, LAW setup) sign-extended addresses
   ≥ 0x80000000 to 64-bit, causing TLB misses. Replaced with LOAD_ADDR32 macro.

2. CCSRBAR TLB1 ordering -- TLB1 Entry 1 was created with the relocated
   CCSRBAR address before the hardware register was actually relocated, breaking
   access to CCSR. Now uses CCSRBAR_DEF initially, then re-creates the TLB1
   entry after relocation completes.

3. TLB1 multi-hit overlap (256 MB flash) -- The flash TLB Entry 2 covering
   0xF0000000-0xFFFFFFFF (256 MB) overlapped with the boot ROM TLB Entry 0 at
   the top of flash, causing an e6500 TLB multi-hit. For BOARD_CW_VPX3152:

   • Boot TLB enlarged to 16 MB (BOOKE_PAGESZ_16M) covering wolfBoot + partitions
   • Flash TLB Entry 2 setup is skipped
   • hal_flash_enable_caching / cache_disable / cache_enable are no-ops
     (boot TLB stays cache-inhibited; functional but slower)

4. hal_mp_init invalidating boot TLB -- disable_tlb1(0) invalidated the
   boot TLB containing wolfBoot code. NAII works because its 256 KB boot TLB
   doesn't contain wolfBoot code (which is in flash TLB Entry 2). For VPX3-152
   the boot TLB IS where wolfBoot runs, so invalidating it faults the next
   instruction fetch. ENABLE_MP is now disabled for VPX3-152.

5. Exception handler used wrong UART address -- isr_empty printed '!' to
   0xFE11C500 (the default CCSRBAR) which is invalid after relocation on
   VPX3-152. Updated to use CCSRBAR + 0x11C500.

6. DTS address unmapped -- hal_get_dts_address() returned 0xF0040000
   which is below the 16 MB boot TLB → DSI fault. Returns NULL for VPX3-152
   until a separate flash TLB for the DTS region is added.

Verification

Tested on physical CW VPX3-152 hardware (RCW 608605-100, 1.8 GHz core, 600 MHz
platform clock, 4 GB DDR3L, 1866 MT/s). wolfBoot now successfully:

• Initializes CCSRBAR, DDR, flash, CPC L3 cache
• Loads boot partition signed image (ECC384 + SHA384)
• Verifies signature
• Copies image to RAM
• Jumps to test app which prints "Test App: idle loop"

Used Pi4 GPIO control + Instek PST-3202 power cycling + PABS U-Boot to flash
wolfBoot via TFTP for the test cycle.

Files

• src/boot_ppc_start.S -- LOAD_ADDR32 fixes, TLB sizing for VPX3, early UART debug helpers
• src/boot_ppc_mp.S -- Minor cleanup
• hal/nxp_t2080.c -- ENABLE_MP guard, cache function guards, DTS NULL for VPX3
• hal/nxp_t2080.h -- DDR_SDRAM_MODE_3..8 individual defines, DDR dump command updates
• docs/Targets.md -- VPX3-152 PABS testing procedure, DDR register dump commands
• .github/workflows/test-configs.yml -- CI build coverage

[Copilot]

Pull request overview

This PR fixes multiple early-boot issues for NXP QorIQ T2080/e6500 targets to enable wolfBoot to boot successfully on the Curtiss‑Wright VPX3‑152 (256 MB NOR @ 0xF0000000, CCSRBAR relocated to 0xEF000000), while keeping NAII 68PPC2 behavior intact.

Changes:

• Corrects high-address loads on e6500 (avoid lis sign-extension) and adjusts TLB1/CCSRBAR relocation sequencing to prevent faults.
• Adds VPX3‑152-specific TLB sizing/mapping changes to avoid TLB multi-hit overlap with 256 MB NOR.
• Updates T2080 HAL for VPX3‑152 constraints (disable MP, guard flash caching paths, DTS address handling) and refreshes DDR configuration constants/docs/CI coverage.

Reviewed changes

Copilot reviewed 6 out of 6 changed files in this pull request and generated 3 comments.

Show a summary per file

File	Description
src/boot_ppc_start.S	e6500-safe address loading, CCSRBAR relocation/TLB ordering fixes, VPX3‑152 TLB sizing & flash mapping adjustments, early UART debug helpers
src/boot_ppc_mp.S	Comment/clarity cleanup in MP boot assembly
hal/nxp_t2080.c	VPX3‑152 MP disable guard, flash caching guards, flash bounds checks, DTS NULL for VPX3‑152, minor synchronization improvements
hal/nxp_t2080.h	Updates DDR parameterization and expands MODE3–8 defines; populates additional RDB register values
docs/Targets.md	Expanded T2080 target documentation: board matrix, VPX3‑152 specifics, programming/recovery notes
.github/workflows/test-configs.yml	Adds board-specific build jobs for T2080 variants in CI

Comments suppressed due to low confidence (1)

hal/nxp_t2080.c:400

• hal_flash_enable_caching() is a no-op for BOARD_CW_VPX3152, but the DEBUG_UART log still prints "Flash: caching enabled" unconditionally. This makes UART logs misleading when debugging VPX3-152 boot/flash performance. Gate the log behind the same #ifndef BOARD_CW_VPX3152, or print an alternate message indicating caching is skipped/uncached on this board.

#ifndef BOARD_CW_VPX3152
    /* Rewrite flash TLB entry with cacheable attributes.
     * MAS2_M = memory coherent, enables caching */
    set_tlb(1, 2,
        FLASH_BASE_ADDR, FLASH_BASE_ADDR, FLASH_BASE_PHYS_HIGH,
        MAS3_SX | MAS3_SW | MAS3_SR, MAS2_M, 0,
        FLASH_TLB_PAGESZ, 1);

    /* Invalidate L1 I-cache so new TLB attributes take effect */
    invalidate_icache();
#endif

#ifdef DEBUG_UART
    wolfBoot_printf("Flash: caching enabled (L1+L2+CPC)\n");
#endif

---

💡 Add Copilot custom instructions for smarter, more guided reviews. Learn how to get started.