[bsp][renesas] fix clock_timer divider setup and sample startup sequence

[illustriousness]

Summary | 变更摘要

• Fix GPT divider programming in CLOCK_TIMER_CTRL_FREQ_SET.

• Correct GTCR.TPCS mapping for RA/FSP divider values.

• Stop timer and unlock/restore GTWP before updating divider.

• Return actual hardware timer frequency to clock_timer core.

• In clock_timer_sample, prefer timer1, clear pending IRQ before
  start, and print callback deltas.

• 修复 CLOCK_TIMER_CTRL_FREQ_SET 中 GPT 分频配置流程。

• 按 RA/FSP 的分频映射正确写入 GTCR.TPCS。

• 更新分频前先停计数器并解锁/恢复 GTWP 写保护。

• 将硬件实际频率回写给 clock_timer 核心。

• 在 clock_timer_sample 中默认使用 timer1，启动前清 pending 中断，
  并打印回调间隔。

Root Cause | 问题根因

The previous divider update path could cause mismatch between software
timeout conversion and hardware effective frequency, resulting in
unexpectedly short callback periods (for example around 10 ms).
旧的分频更新路径会导致软件超时换算与硬件实际频率不一致，从而出现回调周
期异常偏短（例如约 10 ms）。

Validation | 验证结果

• Build passed with scons -j$(nproc) on ra6m3-hmi-board.

• Runtime clock_timer_sample callback interval stabilizes around
  992/993 ms after first callback.

• 在 ra6m3-hmi-board 上执行 scons -j$(nproc) 编译通过。

• 运行 clock_timer_sample 后，首个回调之后间隔稳定在 992/993 ms 左
  右。

Files | 涉及文件

• bsp/renesas/libraries/HAL_Drivers/drivers/drv_timer.c

[github-actions]

📌 Code Review Assignment

🏷️ Tag: bsp_renesas

Reviewers: kurisaW

Changed Files (Click to expand)

• bsp/renesas/libraries/HAL_Drivers/drivers/drv_timer.c

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📊 Current Review Status (Last Updated: 2026-04-08 21:44 CST)

• ⌛ kurisaW Pending Review

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[github-actions]

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[Rbb666]

这块不需要加缩进

[illustriousness]

已修改